1. Field of the Invention
This invention relates to a method of fabricating an integrated circuit and more specifically to a method for reducing the resistance of electrical coupling between conductive layers in vias or contact holes.
2. Background of the Invention
Several factors adversely impact the effectiveness of multilevel interconnects. Among them include, but are not limited to, misalignment of vias or contact holes caused by the via patterning process and the failure to remove resistive compounds formed on electrodes positioned in the misaligned contact holes. These two factors cause an increase in resistance of the contact holes, resulting in poor conduction between the levels of the interconnect. Consequently, the reliability of the produced device is diminished. As VLSI feature sizes continues to shrink, for example to sub 0.25 .mu.m region, the problem of misaligned or "unlanded" vias seem unavoidable. Thus, to improve device performance and reliability, as related to conduction between conductive layers, it would be desirable to reduce or eliminate the presence of the aforementioned resistive compounds.
To pose the problem more concretely by way of example, aluminum (Al) is a preferred material for electrodes because it is lightweight, corrosion resistant, and inexpensive. However, aluminum is porous and has a high effective surface area capable of easily adsorbing oxygen and water vapor. As a result, during the processing of multilevel interconnects, a native oxide layer is formed on the aluminum. The oxidized aluminum acts as a resistive film.
As discussed above, the problem of conductivity is also heightened due to the misalignment of vias or contact holes. Ideally, as illustrated in FIG. 1, the vias 2 should be positioned directly above the aluminum electrodes 4, as depicted by area X. Referring to FIG. 1, there is illustrated a substrate 6 supporting the electrodes 4. An intermediate dielectric layer 8 separates the electrodes 4 from a second level of interconnect 10. The direct alignment of tungsten (W) filled vias 2 on the aluminum electrodes 4 can provide a resistance of about 1 .OMEGA. to about 2 .OMEGA. for the contact holes 2. When the tungsten filled vias 2 are misaligned or "unlanded," generally illustrated by area Y in FIG. 2, the resistance of the contact holes can increase, causing the reliability of the device to suffer.
The combination of having an oxidized aluminum electrodes 4 and misaligned tungsten filled vias 2, therefore, can produce a resistance about 8-10 .OMEGA., for the contact holes 2. This combination is illustrated in FIG. 2. In order to compensate for the increase in resistivity caused by the misalignment of the contact holes 2, the resistance of the aluminum electrode 4 has to be decreased. Therefore, the active conductive contact area (i.e., the area not covered by native oxide) of the aluminum electrode 4 must be enlarged. The only active contact area of aluminum electrode 4 is area D, an area which is typically covered by titanium nitride 5. It is desirable to remove the oxidized aluminum film, as illustrated by shaded area 7, from the aluminum electrode 4, and in effect, to make contact area C active. The activation of contact area C produces a resistivity of about 2 .OMEGA. to about 3 .OMEGA. for the "unlanded" tungsten filled contact holes 2, a decline of about 5 .OMEGA. to about 8 .OMEGA..